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Dynamic logic (digital electronics)

For the subject in theoretical computer science, see dynamic logic (modal logic).

In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinatory logic circuits, particularly those implemented in MOS technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high speed digital electronics, particularly computer CPUs. Dynamic logic circuits are usually faster than static counterparts, and require less surface area, but are more difficult to design. Dynamic logic has a higher toggle rate[clarification needed] than static logic but the capacitive loads being toggled are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g. dynamic CMOS or dynamic SOI design.

Dynamic logic is distinguished from so-called static logic in that dynamic logic uses a clock signal in its implementation of combinational logic circuits. The usual use of a clock signal is to synchronize transitions in sequential logic circuits. For most implementations of combinational logic, a clock signal is not even needed.

The static/dynamic terminology used to refer to combinatorial circuits should not be confused with how the same adjectives are used to distinguish memory devices, e.g. static RAM from dynamic RAM.

Contents

In the context of logic design, the term dynamic logic is more commonly used as compared to clocked logic, as it makes clear the distinction between this type of design and static logic. To additionally confuse the matter, clocked logic is sometimes used as a synonym for sequential logic. This usage is nonstandard and should be avoided.

The largest difference between static and dynamic logic is that in dynamic logic, a clock signal is used to evaluate combinational logic. However, to truly comprehend the importance of this distinction, the reader will need some background on static logic.

In most types of logic design, termed static logic, there is at all times some mechanism to drive the output either high or low. In many of the popular logic styles, such as TTL and traditional CMOS, this principle can be rephrased as a statement that there is always a low-impedance DC path between the output and either the supply voltage or the ground. As a sidenote, there is of course an exception in this definition in the case of high impedance outputs, such as a tri-state buffer; however, even in these cases, the circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic.

In contrast, in dynamic logic, there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle. During the time intervals when the output is not being actively driven, stray capacitance causes it to maintain a level within some tolerance range of the driven level.

Dynamic logic requires a minimum clock rate fast enough that the output state of each dynamic gate is used or refreshed before the charge in the output capacitance leaks out enough to cause the digital state of the output to change, during the part of the clock cycle that the output is not being actively driven.

Static logic has no minimum clock rate—the clock can be paused indefinitely. While it may seem that doing nothing for long periods of time is not particularly useful, it leads to three advantages:

  • being able to pause a system at any time makes debugging and testing much easier, enabling techniques such as single stepping.
  • being able to run a system at extremely low clock rates allows low-power electronics to run longer on a given battery.
  • a fully-static system can instantly resume exactly where it left off; a person doesn't have to wait for the system to boot up or resume.

Being able to pause a system at any time for any duration can also be used to synchronize the CPU to an asynchronous event. (While there are other mechanisms to do this, such as interrupts, polling loops, processor idling input pins [like RDY on the 6502], or processor bus cycle extension mechanisms such as WAIT inputs, using hardware to gate the clock to a static-core CPU is simpler, is more temporally precise, uses no program code memory, and uses almost no power in the CPU while it is waiting. In a basic design, to start waiting, the CPU would write to a register to set a binary latch bit which would be ANDed or ORed with the processor clock, stopping the processor. A signal from a peripheral device would reset this latch, resuming CPU operation. [The hardware logic must gate the latch control inputs as necessary to ensure that a latch output transition does not cause the clock signal level to instantaneously change and cause a clock pulse, either high or low, that is shorter than normal.])

In particular, although many popular CPUs use dynamic logic,[citation needed] only static cores—CPUs designed with fully static technology—are usable in space satellites owing to their higher radiation hardness.[better source needed]

Dynamic logic, when properly designed, can be over twice as fast as static logic. It uses only the faster N transistors, which improve transistor sizing optimizations. Static logic is slower because it has twice the capacitive loading, higher thresholds, and uses slow P transistors for logic. Dynamic logic can be harder to work with, but it may be the only choice when increased processing speed is needed. Most electronics running at over 2 GHz these days[when?] require the use of dynamic logic, although some manufacturers such as Intel have designed chips using completely static logic to reduce power consumption. Note that reducing power use not only extends the running time with limited power sources such as batteries or solar arrays (as in spacecraft), but it also reduces the thermal design requirements, reducing the size of needed heatsinks, fans, etc., which in turn reduces system weight and cost.

In general, dynamic logic greatly increases the number of transistors that are switching at any given time, which increases power consumption over static CMOS. There are several powersaving techniques that can be implemented in a dynamic logic based system. In addition, each rail can convey an arbitrary number of bits, and there are no power-wasting glitches. Power-saving clock gating and asynchronous techniques are much more natural in dynamic logic.

As an example, consider the static logic implementation of a CMOS NAND gate:

This circuit implements the logic function

O u t = A B ¯ {\displaystyle Out={\overline {AB}}}

If A and B are both high, the output will be pulled low. Whereas if either A or B are low, the output will be pulled high. At all times, the output is pulled either low or high.

Consider now a dynamic logic implementation of the same logic function:

The dynamic logic circuit requires two phases. The first phase, when Clock is low, is called the setup phase or the precharge phase and the second phase, when Clock is high, is called the evaluation phase. In the setup phase, the output is driven high unconditionally (no matter the values of the inputs A and B). The capacitor, which represents the load capacitance of this gate, becomes charged. Because the transistor at the bottom is turned off, it is impossible for the output to be driven low during this phase.

During the evaluation phase, Clock is high. If A and B are also high, the output will be pulled low. Otherwise, the output stays high (due to the load capacitance).

Dynamic logic has a few potential problems that static logic does not. For example, if the clock speed is too slow, the output will decay too quickly to be of use. Also, the output is only valid for part of each clock cycle, so the device connected to it must sample it synchronously during the time that it is valid.

Also, when both A and B are high, so that the output is low, the circuit will pump one capacitor-load of charge from Vdd to ground for each clock cycle, by first charging and then discharging the capacitor in each clock cycle. This makes the circuit (with its output connected to a high impedance) less efficient than the static version (which theoretically should not allow any current to flow except through the output), and when the A and B inputs are constant and both high, the dynamic NAND gate uses power in proportion to the clock rate, as long as it functions correctly. The power dissipation can be minimized by keeping the load capacitance low, but this in turn reduces the maximum cycle time, requiring a higher minimum clock frequency; the higher frequency then increases power consumption by the relation just mentioned. Therefore, it is impossible to reduce the idle power consumption (when both inputs are high) below a certain limit which derives from an equilibrium between clock speed and load capacitance.

A popular implementation is domino logic.

  1. Lars Wanhammar (1999). DSP integrated circuits. Academic Press. p. 37. ISBN 978-0-12-734530-7.
  2. Andrew Marshall; Sreedhar Natarajan (2002). SOI design: analog, memory and digital techniques. Springer. p. 125. ISBN 978-0-7923-7640-8.
  3. A. Albert Raj, T. Latha (21 October 2008). VLSI Design. PHI Learning Pvt. Ltd. p. 167. ISBN 978-81-203-3431-1.
  4. Bruce Jacob; Spencer Ng; David Wang (2007). Memory systems: cache, DRAM, disk. Morgan Kaufmann. p. 270. ISBN 978-0-12-379751-3.
  5. David Harris (2001). Skew-tolerant circuit design. Morgan Kaufmann. p. 38. ISBN 978-1-55860-636-4.
  6. Richard Murray. "PocketBook II hardware".
  7. Gülzow, Peter. "No RISC, No Fun!". AMSAT-DL. Translated by Moe, Don. Archived from the original on 13 April 2013. Retrieved15 September 2021.
  8. "The Dark Knight: Intel's Core i7".

General references

  • Sung-Mo Kang; Yusuf Leblebici (2003). CMOS digital integrated circuits: analysis and design (3rd ed.). McGraw-Hill. ISBN 978-0-07-246053-7. Chapter 9, "Dynamic logic circuits" (chapter 7 in the 2nd edition)
  • R. Jacob Baker (2010). CMOS: Circuit Design, Layout, and Simulation (3rd ed.). Wiley-IEEE. ISBN 978-0-470-88132-3. Chapter 14, "Dynamic logic gates"
  • Andrew Marshall; Sreedhar Natarajan (2002). SOI design: analog, memory and digital techniques. Springer. ISBN 978-0-7923-7640-8. Chapter 7, "Dynamic SOI Design"

Dynamic logic (digital electronics)
Dynamic logic digital electronics Language Watch Edit 160 160 Redirected from Static logic digital logic For the subject in theoretical computer science see dynamic logic modal logic In integrated circuit design dynamic logic or sometimes clocked logic is a design methodology in combinatory logic circuits particularly those implemented in MOS technology It is distinguished from the so called static logic by exploiting temporary storage of information in stray and gate capacitances 1 It was popular in the 1970s and has seen a recent resurgence in the design of high speed digital electronics particularly computer CPUs Dynamic logic circuits are usually faster than static counterparts and require less surface area but are more difficult to design Dynamic logic has a higher toggle rate clarification needed than static logic 2 but the capacitive loads being toggled are smaller 3 so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs When referring to a particular logic family the dynamic adjective usually suffices to distinguish the design methodology e g dynamic CMOS 4 or dynamic SOI design 2 Dynamic logic is distinguished from so called static logic in that dynamic logic uses a clock signal in its implementation of combinational logic circuits The usual use of a clock signal is to synchronize transitions in sequential logic circuits For most implementations of combinational logic a clock signal is not even needed The static dynamic terminology used to refer to combinatorial circuits should not be confused with how the same adjectives are used to distinguish memory devices e g static RAM from dynamic RAM 5 Contents 1 Terminology 2 Static versus dynamic logic 3 Static logic example 4 Dynamic logic example 5 See also 6 References 7 External linksTerminology EditIn the context of logic design the term dynamic logic is more commonly used as compared to clocked logic as it makes clear the distinction between this type of design and static logic To additionally confuse the matter clocked logic is sometimes used as a synonym for sequential logic This usage is nonstandard and should be avoided Static versus dynamic logic EditThe largest difference between static and dynamic logic is that in dynamic logic a clock signal is used to evaluate combinational logic However to truly comprehend the importance of this distinction the reader will need some background on static logic In most types of logic design termed static logic there is at all times some mechanism to drive the output either high or low In many of the popular logic styles such as TTL and traditional CMOS this principle can be rephrased as a statement that there is always a low impedance DC path between the output and either the supply voltage or the ground As a sidenote there is of course an exception in this definition in the case of high impedance outputs such as a tri state buffer however even in these cases the circuit is intended to be used within a larger system where some mechanism will drive the output and they do not qualify as distinct from static logic In contrast in dynamic logic there is not always a mechanism driving the output high or low In the most common version of this concept the output is driven high or low during distinct parts of the clock cycle During the time intervals when the output is not being actively driven stray capacitance causes it to maintain a level within some tolerance range of the driven level Dynamic logic requires a minimum clock rate fast enough that the output state of each dynamic gate is used or refreshed before the charge in the output capacitance leaks out enough to cause the digital state of the output to change during the part of the clock cycle that the output is not being actively driven Static logic has no minimum clock rate the clock can be paused indefinitely While it may seem that doing nothing for long periods of time is not particularly useful it leads to three advantages being able to pause a system at any time makes debugging and testing much easier enabling techniques such as single stepping being able to run a system at extremely low clock rates allows low power electronics to run longer on a given battery a fully static system can instantly resume exactly where it left off a person doesn t have to wait for the system to boot up or resume 6 Being able to pause a system at any time for any duration can also be used to synchronize the CPU to an asynchronous event While there are other mechanisms to do this such as interrupts polling loops processor idling input pins like RDY on the 6502 or processor bus cycle extension mechanisms such as WAIT inputs using hardware to gate the clock to a static core CPU is simpler is more temporally precise uses no program code memory and uses almost no power in the CPU while it is waiting In a basic design to start waiting the CPU would write to a register to set a binary latch bit which would be ANDed or ORed with the processor clock stopping the processor A signal from a peripheral device would reset this latch resuming CPU operation The hardware logic must gate the latch control inputs as necessary to ensure that a latch output transition does not cause the clock signal level to instantaneously change and cause a clock pulse either high or low that is shorter than normal In particular although many popular CPUs use dynamic logic citation needed only static cores CPUs designed with fully static technology are usable in space satellites owing to their higher radiation hardness 7 better source needed Dynamic logic when properly designed can be over twice as fast as static logic It uses only the faster N transistors which improve transistor sizing optimizations Static logic is slower because it has twice the capacitive loading higher thresholds and uses slow P transistors for logic Dynamic logic can be harder to work with but it may be the only choice when increased processing speed is needed Most electronics running at over 2 GHz these days when require the use of dynamic logic although some manufacturers such as Intel have designed chips using completely static logic to reduce power consumption 8 Note that reducing power use not only extends the running time with limited power sources such as batteries or solar arrays as in spacecraft but it also reduces the thermal design requirements reducing the size of needed heatsinks fans etc which in turn reduces system weight and cost In general dynamic logic greatly increases the number of transistors that are switching at any given time which increases power consumption over static CMOS 8 There are several powersaving techniques that can be implemented in a dynamic logic based system In addition each rail can convey an arbitrary number of bits and there are no power wasting glitches Power saving clock gating and asynchronous techniques are much more natural in dynamic logic Static logic example EditAs an example consider the static logic implementation of a CMOS NAND gate This circuit implements the logic function O u t A B displaystyle Out overline AB If A and B are both high the output will be pulled low Whereas if either A or B are low the output will be pulled high At all times the output is pulled either low or high Dynamic logic example EditConsider now a dynamic logic implementation of the same logic function The dynamic logic circuit requires two phases The first phase when Clock is low is called the setup phase or the precharge phase and the second phase when Clock is high is called the evaluation phase In the setup phase the output is driven high unconditionally no matter the values of the inputs A and B The capacitor which represents the load capacitance of this gate becomes charged Because the transistor at the bottom is turned off it is impossible for the output to be driven low during this phase During the evaluation phase Clock is high If A and B are also high the output will be pulled low Otherwise the output stays high due to the load capacitance Dynamic logic has a few potential problems that static logic does not For example if the clock speed is too slow the output will decay too quickly to be of use Also the output is only valid for part of each clock cycle so the device connected to it must sample it synchronously during the time that it is valid Also when both A and B are high so that the output is low the circuit will pump one capacitor load of charge from Vdd to ground for each clock cycle by first charging and then discharging the capacitor in each clock cycle This makes the circuit with its output connected to a high impedance less efficient than the static version which theoretically should not allow any current to flow except through the output and when the A and B inputs are constant and both high the dynamic NAND gate uses power in proportion to the clock rate as long as it functions correctly The power dissipation can be minimized by keeping the load capacitance low but this in turn reduces the maximum cycle time requiring a higher minimum clock frequency the higher frequency then increases power consumption by the relation just mentioned Therefore it is impossible to reduce the idle power consumption when both inputs are high below a certain limit which derives from an equilibrium between clock speed and load capacitance A popular implementation is domino logic See also EditDomino logic Sequential logicReferences Edit Lars Wanhammar 1999 DSP integrated circuits Academic Press p 37 ISBN 978 0 12 734530 7 a b Andrew Marshall Sreedhar Natarajan 2002 SOI design analog memory and digital techniques Springer p 125 ISBN 978 0 7923 7640 8 A Albert Raj T Latha 21 October 2008 VLSI Design PHI Learning Pvt Ltd p 167 ISBN 978 81 203 3431 1 Bruce Jacob Spencer Ng David Wang 2007 Memory systems cache DRAM disk Morgan Kaufmann p 270 ISBN 978 0 12 379751 3 David Harris 2001 Skew tolerant circuit design Morgan Kaufmann p 38 ISBN 978 1 55860 636 4 Richard Murray PocketBook II hardware Gulzow Peter No RISC No Fun AMSAT DL Translated by Moe Don Archived from the original on 13 April 2013 Retrieved 15 September 2021 a b The Dark Knight Intel s Core i7 General references Sung Mo Kang Yusuf Leblebici 2003 CMOS digital integrated circuits analysis and design 3rd ed McGraw Hill ISBN 978 0 07 246053 7 Chapter 9 Dynamic logic circuits chapter 7 in the 2nd edition R Jacob Baker 2010 CMOS Circuit Design Layout and Simulation 3rd ed Wiley IEEE ISBN 978 0 470 88132 3 Chapter 14 Dynamic logic gates Andrew Marshall Sreedhar Natarajan 2002 SOI design analog memory and digital techniques Springer ISBN 978 0 7923 7640 8 Chapter 7 Dynamic SOI Design External links EditIntroduction to CMOS VLSI Design Lecture 9 Circuit Families David Harris lecture notes on the subject Retrieved from https en wikipedia org w index php title Dynamic logic digital electronics amp oldid 1044481546 Static versus dynamic logic, wikipedia, wiki, book,

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